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| Freescale Semiconductor Technical Data Document Number: MMA81XXEG Rev 4, 9/2009 Digital X-Axis or Z-Axis Accelerometer The MMA81XXEG (Z-axis) and MMA82XXEG (X-axis) are members of Freescale's family of DSI 2.0-compatible accelerometers. These devices incorporate digital signal processing for filtering, trim and data formatting. Features * Available in 20g, 40g, 50g, 100g, 150g, and 250g (MMA82XXEG, X-axis) and 40g, 100g, 150g, and 250g (MMA81XXEG, Z-axis). Additional g-ranges may be available upon request 80 customer-accessible OTP bits 10-bit digital data output from 8 to 10 bit DSI output 6.3 to 30 V supply voltage On-chip voltage regulator Internal self-test Minimal external component requirements RoHS compliant (-40 to +125C) 16-pin SOIC package Automotive AEC-Q100 qualified DSI 2.0 Compliant Z-axis transducer is overdamped MMA81XXEG MMA82XXEG SERIES SINGLE-AXIS DSI 2.0 ACCELEROMETER * * * * * * * * * * EG SUFFIX (Pb-free) 16-LEAD SOIC CASE 475-01 PIN CONNECTIONS Typical Applications * * * Crash detection (Airbag) Impact and vibration monitoring Shock detection. N/C N/C CREG VPP/TEST CFIL DOUT VGND/DIN CLK 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VSS VSS BUSRTN BUSIN BUSOUT HCAP VSS CREG 16-PIN SOIC PACKAGE (c) Freescale Semiconductor, Inc., 2009. All rights reserved. ORDERING INFORMATION Device Name MMA8225EGR2 MMA8225EG MMA8215EGR2 MMA8215EG MMA8210TEGR2 MMA8210TEG MMA8205TEGR2 MMA8205TEG MMA8204EGR2 MMA8204EG MMA8202EGR2 MMA8202EG MMA8125EGR2 MMA8125EG MMA8115EGR2 MMA8115EG MMA8110EGR2 MMA8110EG MMA8104EGR2 MMA8104EG X-axis g-Level 250 250 150 150 100 100 50 50 40 40 20 20 -- -- -- -- -- -- -- -- Z-axis g-Level -- -- -- -- -- -- -- -- -- -- -- -- 250 250 150 150 100 100 40 40 Temperature Range -40 to +125C -40 to +125C -40 to +125C -40 to +125C -40 to +125C -40 to +125C -40 to +125C -40 to +125C -40 to +125C -40 to +125C -40 to +125C -40 to +125C -40 to +125C -40 to +125C -40 to +125C -40 to +125C -40 to +125C -40 to +125C -40 to +125C -40 to +125C SOIC 16 Package 475-01 475-01 475-01 475-01 475-01 475-01 475-01 475-01 475-01 475-01 475-01 475-01 475-01 475-01 475-01 475-01 475-01 475-01 475-01 475-01 Packaging Tape & Reel Tubes Tape & Reel Tubes Tape & Reel Tubes Tape & Reel Tubes Tape & Reel Tubes Tape & Reel Tubes Tape & Reel Tubes Tape & Reel Tubes Tape & Reel Tubes Tape & Reel Tubes SECTION 1 GENERAL DESCRIPTION MMA81XXEG/MMA82XXEG family is a satellite accelerometer which is comprised of a single axis, variable capacitance sensing element with a single channel interface IC. The interface IC converts the analog signal to a digital format which is transmitted in accordance with the DSI-2.0 specification. 1.1 OVERVIEW Signal conditioning begins with a Capacitance to Voltage conversion (C to V) followed by a 2-stage switched capacitor amplifier. This amplifier has adjustable offset and gain trimming and is followed by a low-pass switched capacitor filter with Bessel function. Offset and gain of the interface IC are trimmed during the manufacturing process. Following the filter the signal passes to the output stage. The output stage sensitivity incorporates temperature compensation. The output of the accelerometer signal conditioning is converted to a digital signal by an A/D converter. After this conversion the resultant digital word is converted to a serial data stream which may be transmitted via the DSI bus. Power for the device is derived from voltage applied to the BUSIN/BUSOUT and VSS pins. Bus voltage is rectified and applied to an external capacitor connected to the HCAP pin. During data transmissions, the device operates from stored charge on the external capacitor. An integrated regulator supplies fixed voltage to internal circuitry. A self-test voltage may be applied to the electrostatic deflection plate in the sensing element. Self-Test voltage is factory trimmed. Other support circuits include a bandgap voltage reference for the bias sources and the self-test voltage. A total of 128 bits of One-Time Programmable (OTP) memory, are provided for storage of factory trim data, serial number and device characteristics. Eighty OTP bits are available for customer programming. These eighty OTP bits may be programmed via the DSI Bus or through the serial test/trim interface. OTP integrity is verified through continuous parity checking. Separate parity bits are provided for factory and customer programmed data. In the event that a parity fault is detected, the reserved value of zero is transmitted in response to a Read Acceleration Data command. A block diagram illustrating the major elements of the device is shown in Figure 1-1. MMA81XXEG 2 Sensors Freescale Semiconductor REGULATOR TRIM 11 VOLTAGE REGULATOR INTERNAL SUPPLY VOLTAGE 9 HCAP CREG 3 12 CREG BUSOUT BUSIN 13 N/C N/C 1 2 VSS VSS VSS BUSRTN BANDGAP REFERENCE 16 15 10 14 GROUND LOSS DETECTOR 7 VGND/DIN OSCILLATOR SELFTEST TRIM OSC TRIM SELFTEST VOLTAGE LOGIC COMMAND DECODE STATE MACHINE RESPONSE GENERATION 4 OTP PROGRAMMING INTERFACE 6 8 VPP/TEST DOUT CLK SELF-TEST ENABLE A-TO-D CONVERTER SWITCHES SHOWN IN NORMAL OPERATING CONFIGURATION g-CELL C-TO-V CONVERTER LOW-PASS FILTER 5 CFIL GAIN TRIM OFFSET TRIM TCS TRIM Figure 1-1. Overall Block Diagram MMA81XXEG Sensors Freescale Semiconductor 3 1.2 PACKAGE PINOUT The pinout for this 16-pin device is shown in Figure 1-2. +Z N/C N/C CREG VPP/TEST CFIL DOUT VGND/DIN CLK 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VSS VSS BUSRTN BUSIN BUSOUT HCAP VSS CREG +X -X -Z ACTIVATION OF Z-AXIS SELF-TEST CAUSES OUTPUT TO BECOME MORE POSITIVE PROJECTION 16-PIN SOIC PACKAGE ACTIVIATION OF X-AXIS SELF-TEST CAUSES OUTPUT TO BECOME MORE POSITIVE CASE: 475-01 N/C: NO INTERNAL CONNECTION Output response to displacement in the direction of arrows. +1 g +1 g 0g 0g 0g 0g -1 g TO CENTER OF GRAVITATIONAL FIELD -1 g Response to static orientation within 1 g field. Figure 1-2. Device Pinout MMA81XXEG 4 Sensors Freescale Semiconductor 1.3 PIN FUNCTIONS The following paragraphs provide descriptions of the general function of each pin. 1.3.1 HCAP and VSS Power is supplied to the ASIC through BUSIN or BUSOUT and BUSRTN. The supply voltage is rectified internally and applied to the HCAP pin. An external capacitor connected to HCAP forms the positive supply for the integrated voltage regulator. VSS is supply return node. All VSS pins are internally connected to BUSRTN. To obtain specified performance, all VSS nodes should be connected to the BUSRTN node on the PWB. To ensure stability of the internal voltage regulator and meet DFMEA requirements, the connection from HCAP to the external capacitor should be as short as possible and should not be routed elsewhere on the printed wiring assembly. The voltage on HCAP is monitored. If the voltage falls below a specified level, the device will return the value zero in response to a short word Read Acceleration Data command, and report the undervoltage condition by setting the Undervoltage (U) flag. Should the undervoltage condition persist for more than one millisecond, the internal Power-On Reset (POR) circuit is activated and the device will not respond until the voltage at HCAP is restored to operating levels and the device has undergone post-reset initialization. 1.3.2 BUSIN The BUSIN pin is normally connected to the DSI bus and supports bidirectional communication with the master. MMA81XXEG supports reverse initialization for improved system fault tolerance. In the event that the DSI bus cannot support communication between the master and BUSIN pin, communication with the master may be conducted via the BUSOUT pin and the BUSIN pin can be used to access other DSI devices. 1.3.3 BUSOUT The BUSOUT pin is normally connected to the DSI bus for daisy-chained bus configurations. In support of fault tolerance at the system level, the BUSOUT pin can be used as an input for reverse initialization and data communication. The internal bus switch is always open following reset. The bus switch is closed when data bit D6 is set when an Initialization or Reverse Initialization command is received. 1.3.4 BUSRTN This pin provides the common return for power and signalling. 1.3.5 CREG The internal voltage regulator requires external capacitance to the VSS pin for stability. This should be a high grade capacitor without excessive internal resistance or inductance. An optional electrolytic capacitor may be required if a longer power down delay is required. Figure 1-3 illustrates the relationship between capacitance, series resistance and voltage regulator stability. Two CREG pins are provided for redundancy. It is recommended that both CREG pins are connected to the external capacitor(s) for best system reliability. STABLE, UNACCEPTABLE NOISE PERFORMANCE 700 m UNSTABLE ESR STABLE 0 1 F CREG Figure 1-3. Voltage Regulator Capacitance and Series Resistance MMA81XXEG Sensors Freescale Semiconductor 5 100 F 1.3.6 CFIL The output of the sensor interface circuitry can be monitored at the CFIL pin. An internal buffer is provided to provide isolation between external signals and the input to the A/D converter. If CFIL monitoring is desired, a low-pass filter and a buffer with high input impedance located as close to this pin as possible are required. The circuit configuration shown in Figure 1-5 is recommended. MMA81XXEG/MMA82XXEG 50 k RIN 1 M CFIL 5 680 pF Figure 1-4. CFIL Filter and Buffer Configuration This pin may be configured as an input to the A/D converter when the MMA81XXEG/MMA82XXEG device is in test mode. Refer to Appendix A for further details regarding test mode operation. 1.3.7 Trim/Test Pins (VPP/TEST, CLK, DOUT) These pins are used for programming the device during manufacturing. These pins have internal pull-up or pull-down devices to drive the input when left unconnected. The following termination is recommended for these pins in the end application: Table 1-1 PIN VPP/TEST CLK DOUT Termination Connect to ground Leave unconnected Leave unconnected CLK may be connected to ground, however this is not advised if the GLDE bit in DEVCFG2 is set, as a short between the adjacent VGND/DIN pin and ground prevents ground loss detection. 1.3.8 GND Detect Pin (VGND/DIN) VGND/DIN may be used to detect an open condition between the satellite module and chassis. The ground loss detector circuit supplies a constant current through VGND/DIN and measures resulting voltage. This determines the resistance between VGND/ DIN and the system's virtual ground. A fault condition is signalled if the resistance exceeds specified limits. This pin has no internal pull-down device and must be connected as shown in Figure 1-5. Ground loss detection circuitry is enabled when the GLDE bit is programmed to a logic `1' state in DEVCFG2. Ground loss detection is not available when the master operates in differential mode. VGND/DIN must be directly connected to BUSRTN if the DSI bus is configured for differential operation. VGND/DIN connection options are illustrated in Figure 1-5. When ground loss detection is enabled, a constant current is sourced and the voltage at VGND is continuously monitored. An open connection between VSS and chassis ground will cause the voltage to rise. If the voltage indicates that the connection between chassis ground and VSS has opened, a 14-bit counter is enabled. This counter will reverse if the voltage falls below the detection threshold. Should the counter overflow, a ground loss condition is indicated. The counter acts as a digital low-pass filter, to provide immunity from spurious signals. This pin functions as the SPI data input when the device is in test mode. MMA81XXEG 6 Sensors Freescale Semiconductor GROUND-LOSS DETECTION DISABLED MMA81XXEG/MMA82XXEG 1 2 3 4 5 6 7 8 GROUND-LOSS DETECTION ENABLED (SINGLE-ENDED SYSTEMS ONLY) MMA81XXEG/MMA82XXEG 1 2 3 4 5 6 N/C N/C CREG VPP/TEST CFIL DOUT VGND/DIN CLK VSS VSS BUSRTN BUSIN BUSOUT HCAP VSS CREG 16 15 14 13 12 11 10 9 N/C N/C CREG VPP/TEST CFIL DOUT VGND/DIN CLK VSS VSS BUSRTN BUSIN BUSOUT HCAP VSS CREG 16 15 14 13 12 11 10 9 BUSRTN BUSRTN 7 8 1.00 k, 1% CHASSIS 1 nF Figure 1-5. VGND/DIN Connection Options 1.4 MODULE INTERCONNECT A typical satellite module configuration supporting daisy-chain configuration is shown in Figure 1-6. Capacitors C1 and C2 form a filter network for the internal voltage regulator. Two capacitors are shown for redundancy; this configuration improves reliability in the event of an open capacitor connection. A single 1 F capacitor may be used in place of C1 and C2, however connection from the capacitor to both CREG pins is required. CHOLD stores energy during signal transitions on BUSIN and BUSOUT. The value of this capacitor is typically 1 F; however, this depends upon data rates and bus utilization. MMA81XXEG/MMA82XXEG 1 2 3 4 SEE NOTE N/C 5 6 7 8 N/C N/C CREG VPP/TEST CFIL DOUT VGND/DIN CLK VSS VSS BUSRTN BUSIN BUSOUT HCAP VSS CREG 16 15 14 13 12 11 10 9 BUSIN BUSOUT C1 1 F C2 1 F CHOLD BUSRTN NOTE: LEAVE OPEN OR CONNECT TO SIGNAL MONITOR. Figure 1-6. Typical Satellite Module Diagram 1.5 DEVICE IDENTIFICATION Thirty-two OTP bits are factory-programmed with a unique serial number during the manufacturing and test. Five additional bits are factory-programmed to indicate the full-scale range and axis of sensitivity. Device identification data may be read at any time while the device is active. MMA81XXEG Sensors Freescale Semiconductor 7 SECTION 2 SUPPORT MODULES 2.1 MASTER OSCILLATOR A temperature-compensated internal oscillator provides a stable timing reference for the device. The oscillator is factory-trimmed to operate at a nominal frequency of 4 MHz. 2.2 VOLTAGE REGULATION The internal voltage regulator has minimum voltage level detection, which will hold the device in reset and prevent data transmission should the regulator output fall during operation. The regulator also has an input voltage clamp to limit the power dissipated in the regulator during voltage spikes on the HCAP pin which might come from the two or three wire satellite bus. 2.3 BESSEL FILTER 180-Hz, 2-pole and 400 Hz 4-pole Bessel filter options are provided. The low-pass filter is implemented within a two stage switched capacitor amplifier. The overall gain of the Bessel filter is set to a fixed value. The output of the Bessel filter output acts as the input to the A/D converter and is also buffered and made available at the CFIL pin. 2.4 STATUS MONITORING A number of abnormal conditions are detected by MMA81XXEG/MMA82XXEG and the behavior of the device altered if a fault is detected. Detected fault conditions and consequent device behavior is summarized in the table below. Certain conditions, e.g. ground loss, are qualified by device configuration. Figure 2-1 provides a representation of fault conditions, applicable qualifiers and effects. Table 2-1 Fault Condition Response Summary Condition Undervoltage, CREG Sustained Undervoltage, HCAP Frame Timeout Transient Undervoltage, HCAP Fuse Fault Parity Fault Ground Fault Description Internally regulated voltage below operating level Voltage at HCAP below operating level for more than 1 ms Bus voltage remains below frame threshold (tTO) longer than specified time. Voltage at HCAP below operating level for less Undervoltage (U) flag set, short-word Read than 1 ms Acceleration Data response value equals zero OTP fuse threshold failure Parity failure detected in factory or customer programmed OTP data Ground loss detected for more than 4.096 ms Accelerometer Status (S) flag set, short-word Read Acceleration Data response value equals zero Device Behavior Device continuously undergoes reset, bus switch open, no response to DSI commands Accelerometer Status (S) and Ground Fault (GF) flags set, short-word Read Acceleration Data response value equals zero MMA81XXEG 8 Sensors Freescale Semiconductor ST STDIS 1 DDIS FUSE ERROR GF GLDE LOCK1 PAR1 FAULT LOCK2 PAR2 FAULT TRANSIENT UNDERVOLTAGE CONDITION D Q R S SHORT WORD ACCELERATION DATA = 0 U KEY: DDIS FUSE FAULT GLDE GF LOCK1 LOCK2 PAR1 FAULT PAR2 FAULT S ST STDIS U DEVICE DISABLE BIT, DEVCFG2[4] OTP FUSE THRESHOLD FAILURE GROUND LOSS DETECTION BIT, DEVCFG2[5] GROUND FAULT DETECTION CONDITION FACTORY PROGRAMMED OTP LOCK BIT CUSTOMER PROGRAMMED OTP LOCK BIT FACTORY PROGRAMMED OTP PARITY FAULT CONDITION CUSTOMER PROGRAMMED OTP PARITY FAULT CONDITION ACCELEROMETER STATUS FLAG SELF-TEST ACTIVATION CONDITION SELF-TEST DISABLE UNDERVOLTAGE FLAG Figure 2-1. Status Logic Representation The signal STDIS in Figure 2-1 is set when self-test lockout is activated through the execution of two consecutive Disable SelfTest Stimulus commands, as described in Section 4.6.6. If self-test lockout has been activated, a DSI Clear command or poweron reset is required to clear a fault condition which results in reset of the D flip-flop. MMA81XXEG Sensors Freescale Semiconductor 9 SECTION 3 OTP MEMORY MMA81XXEG/MMA82XXEG family features One-Time-Programmable (OTP) memory implemented via a fuse array. OTP is organized as an array of 96 bits which contains the trim data, configuration data, and serial number for each device. Sixteen bits of the OTP array may be programmed by the customer through the DSI Bus. 3.1 INTERNAL REGISTER ARRAY AND OTP MEMORY Contents of OTP memory are transferred to a set of registers following power-on reset, after which the OTP array is powereddown. Contents of the register array are static and may be read at any time following the transfer of data from the OTP memory. Write operations to OTP mirror registers are supported when the device is in test mode, however any data stored in the register will be lost when the device is powered down. The mirror registers are also restored when an OTP read operation is performed. In addition to the registers which mirror OTP memory contents, several other registers are provided. Among these are the OTP Control Registers which controls OTP programming operations and may be used to restore the registers from the OTP memory. CLK DOUT DIN SERIAL PERIPHERAL INTERFACE REGISTER ARRAY TO DIGITAL INTERFACE VPP/TEST OTP ARRAY Figure 3-1. OTP Interface Overview 3.2 OTP WORD ASSIGNMENT Customer-accessible OTP bits are shown in Table 3-1. Unprogrammed OTP bits are read as logic `0' values. DEVCFG1, DEVCFG2 and registers REG-8 through REG-F are programmed by the customer. Other bits are programmed and locked during manufacturing. There is no requirement to program any bits in DEVCFG1 or DEVCFG2 for the device to be fully operational. Table 3-1 Customer Accessible Data Location Address $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F Register SN0 SN1 SN2 SN3 TYPE RESERVED DEVCFG1 DEVCFG2 REG-8 REG-9 REG-A REG-B REG-C REG-D REG-E REG-F LOCK2 PAR2 7 S7 S15 S23 S31 ORDER 0 6 S6 S14 S22 S30 0 0 5 S5 S13 S21 S29 AXIS 0 Customer Defined GLDE DDIS AD3 AD2 Bit Function 4 S4 S12 S20 S28 0 0 3 S3 S11 S19 S27 0 0 2 S2 S10 S18 S26 RNG2 0 1 S1 S9 S17 S25 RNG1 0 AT1 AD1 0 S0 S8 S16 S24 RNG0 0 AT0 AD0 Customer Defined Customer Defined Customer Defined Customer Defined Customer Defined Customer Defined Customer Defined Customer Defined MMA81XXEG 10 Sensors Freescale Semiconductor 3.2.1 Device Serial Number A unique serial number is programmed into each device during manufacturing. The serial number is composed of the following information. Table 3-2 Serial Number Assignment Bit Range S12 - S0 S31 - S13 Content Serial Number Lot Number Lot numbers begin at 1 for all devices produced and are sequentially assigned. Serial numbers begin at 1 for each lot, and are sequentially assigned. No lot will contain more devices than can be uniquely identified by the 13-bit serial number. Not all allowable lot numbers and serial numbers will be assigned. 3.2.2 Type Byte The Type Byte is programmed at final trim and test to indicate the axis of orientation of the g-cell and the calibrated range of the device. Table 3-3 Device Type Register Location Address $04 Register TYPE 7 ORDER 6 0 5 AXIS Bit Function 4 0 3 0 2 RNG2 1 RNG1 0 RNG0 3.2.2.1 Filter Characteristic Bit (ORDER) This bit denotes the low-pass filter characteristic. 0 - 400 Hz, 4-pole 1 - 180 Hz, 2-pole 3.2.2.2 Bit 6 Bit 6 is reserved. It will always be read as a logic `0' value. 3.2.2.3 0 - Z-axis 1 - X-axis 3.2.2.4 Bit 4, Bit 3 Axis of Sensitivity Bit (AXIS) The AXIS bit indicates direction of sensitivity Bit 4 and Bit 3 are reserved. They will always be read as a logic `0' value. 3.2.2.5 Full-Scale Range Bits (RNG2 - RNG0) These three bits define the calibrated range of the device as follows: Table 3-4 RNG2 0 0 0 0 1 1 1 1 RNG1 0 0 1 1 0 0 1 1 RNG0 0 1 0 1 0 1 0 1 Range Unused 20g 40g 50g 100g 150g 250g Unused MMA81XXEG Sensors Freescale Semiconductor 11 3.2.3 Configuration Bytes Two customer-programmable configuration bytes are assigned. 3.2.4 Device Configuration Byte 1 (DEVCFG1) Table 3-5 Device Configuration Byte 1 Location Bit Function 7 6 5 Customer Defined 4 3 2 1 ATT1 0 ATT0 Address $06 Register DEVCFG1 Configuration Byte 1 contains three defined bit functions, plus five bits that can be programmed by the customer to designate any coding desired for packaging axis, model, etc. 3.2.5 Attribute Bits (AT1, AT0) These bits may be assigned by the customer as desired. They are transmitted by MMA81XXEG/MMA82XXEG in response to Request Status, Disable Self-Test Stimulus or Enable Self-Test Stimulus commands, as described in Section 4. 3.2.6 Device Configuration Byte 2 (DEVCFG2) Table 3-6 Device Configuration Byte 2 Location Bit Function 7 LOCK2 6 PAR2 5 GLDE 4 DDIS 3 AD3 2 AD2 1 AD1 0 AD0 Address $07 Register DEVCFG2 Configuration Byte 2 contains six bits that can be programmed by the customer to control device configuration, along with parity and lock bits for DEVCFG1 and DEVCFG2. 3.2.6.1 Customer Data Lock Bit (LOCK2) The bits in configuration bytes 1 and 2 are frozen when the LOCK2 bit is programmed. The LOCK2 bit is not included in the parity check. Locking does not take effect after this bit is programmed until the device has been subsequently reset. 0 - Customer-programmed data area unlocked. 1 - Programming operations inhibited. The DDIS bit is not affected by LOCK2 and may be programmed at any time. 3.2.6.2 Customer Data Parity Bit (PAR2) The PAR2 parity bit is used for detecting changes in configuration bytes 1 and 2 along with registers REG-8 through REG-F (addresses $06 through $0F, inclusive). A fault condition is indicated if a change to parity-protected register data is detected. The PAR2 bit follows an "even" parity scheme (number of logical HIGH bits including parity bit is even). If an internal parity error is detected, the device will respond to Read Acceleration Data commands with zero in the data field, as described in Section 4.5.4. The Status (S) bit will be set in either short word or long word responses to indicate the fault condition. A parity fault may result from a bit failure within the OTP or the registers which store an image of the OTP during operation. In the latter case, power-on reset will clear the fault when the registers are re-loaded. A parity fault associated with the OTP array is a non-recoverable failure. The parity status of customer programmed data is not monitored if the LOCK2 bit is not programmed to a logic `1' state. 3.2.6.3 Ground Loss Detection Enable (GLDE) When this bit is programmed to a logic `1' value, ground loss errors will be reported if a ground fault condition is detected. 1 - Ground-loss detection circuitry enabled 0 - Ground-loss detection disabled. MMA81XXEG 12 Sensors Freescale Semiconductor 3.2.6.4 Device Disable Bit (DDIS) This bit may be programmed at any time, regardless of the state of LOCK2. This bit is intended to be programmed when a module has been determined by the DSI Bus Master to be defective. Programming this bit after LOCK2 has been set will cause the device to respond to short word Read Acceleration Data commands with a zero response. Acceleration results are not affected by this bit when long word Read Acceleration Data commands are executed, however the Status (S) bit will be set in the response. 1 - Device responds to Read Acceleration Data command with zero value 0 - Device responds normally to Read Acceleration Data command 3.2.6.5 Device Address (AD3 - AD0) These bits define the pre-programmed DSI Bus device address. 3.3 OTP PROGRAMMING Two different methods of programming the eighty customer defined bits are supported. In test mode, these may be programmed in the same manner as factory programmed OTP bits. Additionally, the Read Write NVM DSI bus command may be used. Test mode programming operations are described in Appendix A.3. Read Write NVM command operation is described in Section 4.6.3. MMA81XXEG Sensors Freescale Semiconductor 13 SECTION 4 PHYSICAL LAYER AND PROTOCOL MMA81XXEG/MMA82XXEG family is compliant with the DSI Bus Standard, Version 2.0. MMA81XXEG/MMA82XXEG is designed to be compatible with either DSI Version 2 or DSI Version 1.1 compliant bus masters. 4.1 4.2 DSI NETWORK PHYSICAL LAYER INTERFACE DSI NETWORK DATA LINK LAYER Refer to Section 3 of the DSI Bus Standard for information regarding the physical layer interface. Refer to Section 4 of the DSI Bus Standard for information regarding the DSI network data link layer interface. Both standard and enhanced command structures are supported for short word and long word commands. 4.3 DSI BUS COMMANDS DSI Bus Commands which are recognized by MMA81XXEG and the MMA82XXEG are summarized in Table 4-1. Detailed descriptions of each supported command are described in subsequent sections of this document. If a CRC error is detected, or a reserved or unimplemented command is received, the device will not respond. Following all messages, MMA81XXEG and the MMA82XXEG disregards the DSI bus voltage level for approximately 18.5 s. Within this time, all supported commands except Initialization and Reverse Initialization are guaranteed to be executed and the device will be ready for the next message. When the bus voltage falls below the signal high logic level (see Section 5) after the 18.5 s period has elapsed, the device will respond as appropriate to a command sent to it in the previous message. Exactly one response is attempted; if a noise spike or corrupted transfer occurs, the response is not retried. If an Initialization or Reverse Initialization command is executed and the Bus Switch (BS) bit is set, MMA81XXEG and MMA82XXEG will disregard the bus voltage level for a nominal period of 180 s. This interval allows for the bus voltage to recover following closure of the bus switch, while the hold capacitor of a downstream slave charges. Table 4-1 DSI Bus Command Summary Command Data Binary Hex C3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 C2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 C0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $D $E $F Initialization Request Status Read Acceleration Data Not Implemented Request ID Information Not Implemented Not Implemented Clear Not Implemented Read Write NVM Format Control Read Register Data Disable Self-Test Stimulus Activate Self-Test Stimulus Reserved Reverse Initialization LW SW SW N/A SW N/A N/A SW N/A LW LW LW SW SW N/A LW NV BS B1 RA3 R/W 0 -- -- RA2 FA2 0 -- -- RA1 FA1 0 -- -- -- -- -- -- -- -- Description D7 NV -- -- D6 BS -- -- D5 B1 -- -- D4 B0 -- -- D3 PA3 -- -- D2 PA2 -- -- D1 PA1 -- -- D0 PA0 -- -- Size Not Applicable -- -- -- -- -- Not Applicable Not Applicable -- -- -- -- -- Not Applicable RA0 FA0 0 -- -- RD3 FD3 RA3 -- -- RD2 FD2 RA2 -- -- RD1 FD1 RA1 -- -- RD0 FD0 RA0 -- -- Not Applicable B0 PA3 PA2 PA1 PA0 Legend: BS: Bus Switch Control (0: open, 1: close) NV: Nonvolatile memory control (1: program NVM) PA3 - PA0: Device address assigned during Initialization or Reverse Initialization RA3 - RA0: Internal user data register address FA2 - FA0: Format register address FD3 - FD0: Format register data content MMA81XXEG 14 Sensors Freescale Semiconductor 4.4 COMMAND RESPONSE SUMMARIES The device incorporates an analog-to-digital converter which translates the low-pass filtered acceleration signal to a 10-bit binary value. The 10-bit digital result is referred to as AD9 through AD0 in the response tables which follow. 4.4.1 Short Word Response Summary Short word responses for all commands are summarized below. Detailed DSI command descriptions may be found in Section 4.5. Table 4-2 Short-Word Response Summary Command Hex $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $D $E $F Description Initialization Request Status Read Acceleration Data Not Implemented Request ID Information Not Implemented Not Implemented Clear Not Implemented Read/Write NVM Format Control Read Register Data Disable Self-Test Stimulus Activate Self-Test Stimulus Reserved Reverse Initialization NV NV U U ST ST V2 V1 V0 NV U ST D7 D6 D5 Response D4 D3 D2 D1 D0 Not Applicable BS AT1 AT0 S GF See Section 4.5.4 No Response 0 0 1 0 0 No Response No Response No Response No Response Not Valid Not Valid Not Valid BS BS AT1 AT1 AT0 AT0 S S GF GF No Response Not Valid Legend: AT1 - AT0: Attribute codes (see Section 4.5.1.3) NV: State of fuse program control bit BS: State of Bus Switch (0: open, 1: closed) S: Accelerometer status flag (1: internal error) ST: Self-Test flag (1: self-test active) U - Undervoltage condition V2 - V0: Version ID MMA81XXEG Sensors Freescale Semiconductor 15 4.4.2 Long Word Response Summary Long word responses for all commands are summarized below. Detailed DSI command descriptions may be found in Section 4.5. Table 4-3 Long-Word Response Summary Command Hex $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $D $E $F Description Initialization Request Status Read Acceleration Data Not Implemented Request ID Information Not Implemented Not Implemented Clear Not Implemented Read/Write NVM Format Control Read Register Data Disable Self-Test Stimulus Activate Self-Test Stimulus Reserved Reverse Initialization A3 A2 A1 A0 0 0 0 A3 A3 A3 A3 A3 A2 A2 A2 A2 A2 A1 A1 A1 A1 A1 A0 A0 A0 A0 A0 0 1 1 0 A3 A2 A1 A0 0 0 0 D15 A3 A3 A3 D14 A2 A2 A2 D13 A1 A1 A1 D12 A0 A0 A0 D11 0 0 GF D10 0 0 S D9 0 0 Response D8 BF 0 D7 NV NV D6 BS U D5 B1 ST D4 B0 BS D3 D2 D1 D0 PA3 PA2 PA1 PA0 AT1 AT0 S GF AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 No Response 0 V2 V1 V0 0 0 1 0 0 No Response No Response No Response No Response See Section 4.6.3 R/W FA2 FA1 FA0 FD3 FD2 FD1 FD0 RA3 RA2 RA1 RA0 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 0 0 0 0 0 0 0 0 NV NV U U ST ST BS BS AT1 AT1 AT0 AT0 S S GF GF No Response BF NV BS B1 B0 PA3 PA2 PA1 PA0 Legend: A3 - A0: Device address AD9 - AD0: 10-bit acceleration data result AT1 - AT0: Attribute codes (see Section 4.5.1.3) BF: Bus Fault flag (1: bus fault) BS: State of Bus Switch (0: open, 1: closed) FA2 - FA0: Format register address FD3 - FD0: Format register data content GF: Ground fault detected NV: State of fuse program control bit PA3 - PA0: Device address assigned during Initialization/Reverse Initialization RA3 - RA 0: Internal user data register address RD7 - RD0: Internal user data register contents R/W: Read/Write flag for Format Control Register access S: Accelerometer Status Flag (1: internal error) ST: Self-Test Flag (1: self-test active) U - Undervoltage condition V2 - V0: Version ID MMA81XXEG 16 Sensors Freescale Semiconductor 4.5 DSI COMMAND DETAIL Detailed descriptions of command formats and responses are provided in this section. 4.5.1 DSI COMMAND AND RESPONSE BIT DESCRIPTIONS The following abbreviations are used in the descriptions of DSI commands and responses. 4.5.1.1 DSI Device Address - (A3 - A0) DSI device address. This address will be set to the pre-programmed device address following reset, or zero if no pre-programmed address has been assigned. If zero, the device address may be assigned during initialization or reverse initialization. 4.5.1.2 Acceleration Data - (AD9 - AD0) Ten-bit acceleration result produced by the device. This value is returned by the Read Acceleration Data command, described in Section 4.5.4. 4.5.1.3 Attribute Code Bits (AT1, AT0) These bits indicate the contents of DEVCFG1 bits 1 and 0 in response to a Request Status, Activate Self-Test Stimulus or Disable Self-Test Stimulus command. Table 4-4 Attribute Code Bit Assignments LOCK2 0 1 DEVGFG1[1] X 0 0 1 1 DEVGFG1[0] X 0 1 0 1 AT1 1 0 0 1 1 AT0 0 0 1 0 1 4.5.1.4 Bank Select (B1, B0) These bits are assigned during initialization or reverse initialization to select specific fields within the customer accessible data registers. Bank selection affects Read/Write NVM command operation. Invalid combinations of B1 and B0 result in no response from the device to the associated initialization or reverse initialization command. Refer to Section 4.6.3 for further details regarding register programming and bank selection. 4.5.1.5 Bus Fault Bit (BF) This bit indicates the success or failure of the bus test which is performed as part of an Initialization or Reverse Initialization command. 1 - Bus fault detected 0 - Bus test passed 4.5.1.6 Bus Switch Control/Status Bit (BS) This bit controls the state of the bus switch during an Initialization or Reverse Initialization command. It also indicates the state of the bus switch in response to the Initialization, Request Status, Disable Self-Test Stimulus, Activate Self-Test Stimulus and Reverse Initialization commands. 1 - Close bus switch, or bus switch closed 0 - Leave bus switch open, or bus switch opened 4.5.1.7 Format Control Register Address (FA2 - FA0) This three-bit field selects one of eight format control registers. Format control registers are described in Section 4.6.4.3. 4.5.1.8 Format Register Data (FD3 - FD0) Contents of a format control register. This is the data to be written to the register by a Format Control command, or the contents read from the register in response to a Format Control command. MMA81XXEG Sensors Freescale Semiconductor 17 4.5.1.9 Ground Fault Flag (GF) If ground loss detection has been enabled and a ground fault condition is detected, this bit will be set in the response to Request Status, Read Acceleration Data, Disable Self-Test Stimulus or Activate Self-Test Stimulus commands. If ground loss detection is not enabled, this bit will always be read as a logic `0' value. 1 - Ground fault condition detected 0 - Ground connection within specified limits, or ground loss detection disabled. 4.5.1.10 Nonvolatile Memory Program Control Bit (NV) This bit enables programming of customer-programmed OTP locations when set during an Initialization or Reverse Initialization command. Data to be programmed are transferred to the device during subsequent Read Write NVM commands. 1 - Enable OTP programming 0 - OTP programming circuitry disabled 4.5.1.11 Assigned Device Address (PA3 - PA0) This field contains the device address to be assigned during an Initialization or Reverse Initialization command. The address assigned is reported by the device in response to the Initialization or Reverse Initialization command. 4.5.1.12 Register Address (RA3 - RA0) This field determines the register associated with a Read Write NVM or Read Register Data command. The two Bank Select bits (B1, B0) are used to additionally specify a nibble or bit when a Read Write NVM command is executed. 4.5.1.13 Register Data (RD7 - RD0) RD3 - RD0 contain data to be written to an OTP location when a Read Write NVM command is executed if the NV bit is set. RD3 - RD0 contain the data read from the selected register in response to a Read Write NVM command if the NV bit is cleared. RD7 - RD0 indicate the contents of the selected register in response to a Read Register Data command. 4.5.1.14 Format Control Register Read/Write Bit (R/W) This bit controls the operation performed by a Format Control command. 1 - Write Format Control register selected by FA2 - FA0 0 - Read Format Control register unless global command 4.5.1.15 Accelerometer Status Flag (S) This bit provides a cumulative indication of the various error conditions which are monitored by the device. 1 - Either one or more error conditions have been detected and/or the internal Self-Test stimulus circuitry is active 0 - No error condition has been detected The following conditions will cause the status flag to be set: *Internal Self-Test stimulus circuitry is active OTP array parity fault OTP fuse threshold fault (partially-programmed fuse) Transient undervoltage condition Ground fault (if GLDE bit in DEVCFG2 is set) 4.5.1.16 Self-Test State (ST) This bit indicates whether internal self-test stimulus circuitry is active in response to Request Status, Disable Self-Test Stimulus and Activate Self-Test Stimulus commands. 1 - Self-Test stimulus active 0 - Self-Test stimulus disabled 4.5.1.17 Undervoltage Flag (U) This flag is set if the voltage at HCAP is below a specified threshold. Refer to Section 1.3.1 and Section 5 for further details. MMA81XXEG 18 Sensors Freescale Semiconductor 4.5.2 Initialization Command The initialization command conforms to the description provided in Section 6.2.1 of the DSI Bus Standard, Version 2.0. At powerup the device is fully compliant with the DSI 1.1 protocol. The initialization command must be transmitted as a DSI 1.1 compliant long command structure. Features of the DSI 2.0 protocol can not be accessed until a valid DSI 1.1 compliant initialization sequence is performed and the enhanced mode format registers are properly configured. Table 4-5 Initialization Command Structure Data D7 NV D6 BS D5 B1 D4 B0 D3 PA3 D2 PA2 D1 PA1 D0 PA0 A3 A3 Address A2 A2 A1 A1 A0 A0 C3 0 Command C2 0 C1 0 C0 0 4 bits CRC Figure 4-1 illustrates the sequence of operations performed following negation of internal Power-On Reset (POR) and execution of a DSI Initialization command. Initialization commands are recognized only at BUSIN. The BUSOUT node is tested for a bus short to battery high voltage condition, and the Bus Fault (BF) flag set if an error condition is detected. If no bus fault condition is detected and the BS bit is set in the command structure, the bus switch will be closed. If the BS bit is set, the DSI bus voltage level is disregarded for approximately 180 s following initialization to allow the hold capacitor on a downstream slave to charge. If the device has been pre-programmed, PA3 - PA0 and A3 - A0 must match the pre-programmed address. If no device address has been previously programmed into the OTP array, PA3 - PA0 contain the device address, while A3 - A0 must be zero. If any addressing condition is not met, the device address is not assigned, the bus switch will remain open and the device will not respond to the Initialization command. Table 4-6 Initialization Command Response Data D15 A3 D14 A2 D13 A1 D12 A0 D11 0 D10 0 D9 0 D8 BF D7 NV D6 BS D5 B1 D4 B0 D3 A3 D2 A2 D1 A1 D0 A0 4 bits CRC In the response, bits D15 - D12 and D3 - D0 will contain the device address. If the device was unprogrammed when the initialization command was issued, the device address is assigned as the command executes. Both fields will contain the value PA3 - PA0 to indicate successful device address assignment. Initialization or reverse initialization commands which attempt to assign device address zero are ignored. MMA81XXEG Sensors Freescale Semiconductor 19 POR NEGATED LOAD REGISTERS FROM FUSE ARRAY INITIALIZATION COMMAND AT BUSIN? Y N N N REVERSE INITIALIZATION COMMAND AT BUSOUT? Y BS == 1? Y ENABLE IRESP CURRENT DRIVE AT BUSOUT N BS == 1? Y DELAY 10 s ENABLE IRESP CURRENT DRIVE AT BUSIN MEASURE BUSOUT VOLTAGE DELAY 10 s VBUSOUT < VTHH? N SET BF FLAG MEASURE BUSIN VOLTAGE Y CLOSE BUS SWITCH SET BF FLAG N VBUSIN < VTHH? Y CLOSE BUS SWITCH WAIT FOR NEXT DSI BUS COMMAND Figure 4-1. Initialization Sequence MMA81XXEG 20 Sensors Freescale Semiconductor 4.5.3 Request Status Command The Request Status command may be transmitted as either a DSI long command structure or a DSI short command structure of any length. The data field in the command structure is ignored but is included in the CRC calculation. No action is taken if this command is sent to the DSI Global Device Address. Table 4-1 Request Status Command Structure Address A3 A3 A2 A2 A1 A1 A0 A0 C3 0 Command CRC C2 0 C1 0 C0 1 0 to 8 bits Table 4-2 Short Response Structure - Request Status Command Response Length 8 9 10 11 12 13 14 15 Response D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 NV U ST BS AT1 AT0 S GF Table 4-3 Long Response Structure - Request Status Command Data CRC D15 A3 D14 A2 D13 A1 D12 A0 D11 0 D10 0 D9 0 D8 0 D7 NV D6 U D5 ST D4 BS D3 AT1 D2 AT0 D1 S D0 GF 0 to 8 bits 4.5.4 Read Acceleration Data Command The Read Acceleration Data command may be transmitted as either a DSI long command structure or a DSI short command structure of any length. The data field in the command structure is ignored but is included in the CRC calculation. No action is taken if this command is sent to the DSI Global Device Address. Table 4-4 Read Acceleration Data Command Structure Address A3 A3 A2 A2 A1 A1 A0 A0 C3 0 Command CRC C2 0 C1 1 C0 0 0 to 8 bits Table 4-5 Short Response Structure - Read Acceleration Data Command Response Length 8 9 Response D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 MMA81XXEG Sensors Freescale Semiconductor 21 Table 4-5 Short Response Structure - Read Acceleration Data Command Response Length 10 11 12 13 14 15 Response D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DEVCFG1[1] DEVCFG1[0] ST GF S AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Table 4-6 Long Response Structure - Read Acceleration Data Command Data CRC D15 A3 D14 A2 D13 A1 D12 A0 D11 GF D10 S D9 AD9 D8 AD8 D7 AD7 D6 AD6 D5 AD5 D4 AD4 D3 AD3 D2 AD2 D1 AD1 D0 AD0 0 to 8 bits Data returned in response to a Read Acceleration Data command varies, as illustrated in Table 4-5 and Table 4-6. The result is also affected by the state of the self-test circuitry and internal parity. If the self-test circuitry is enabled, the ST bit will be set in data bit D12 of a short word response. If a transient undervoltage condition, parity fault, ground fault or device disable condition exists, the reserved data value of zero will be reported in response to a short word command structure to indicate that a fault condition has been detected. The data value is not affected by a fault condition when a long word response is reported, however the S and GF bits will be set as appropriate. If the self-test circuitry is active, acceleration data is reported regardless of parity faults. The Status (S) bit will be set in either short word or long word responses if a parity fault is detected. 4.5.4.1 ACCELERATION DATA REPRESENTATION Acceleration values may be determined from the 10-bit digital output (DV) as follows: a = sensitivity x (DV - 512) Sensitivity is determined by nominal full-scale range (FSR), linear range of digital values and a scaling factor to compensate for sensitivity error. The linear range of digital values for MMA81XXEG/MMA82XXEG is 1 to 1023. The digital value of 0 is reserved as an error indicator. For the linear ranges of digital values indicated, the nominal value of 1 LSB for each full-scale range is shown in the table below. Table 4-7 Nominal Sensitivity (10-bit data) Full-Scale Range (g) 250 150 100 50 40 20 Nominal Sensitivity (g/digit) 0.61 0.366 0.244 0.122 0.0976 0.0488 MMA81XXEG 22 Sensors Freescale Semiconductor 4.6 ACCELERATION MEASUREMENT TIMING Upon verification of the CRC associated with a Read Acceleration Data command, MMA81XXEG/MMA82XXEG initiates an analog-to-digital conversion. The conversion occurs during the inter frame separation (IFS) and involves a delay during which the BUSIN line is allowed to stabilize, a sample period and finally the translation of the analog signal level to a digital result. 4.6.1 Request ID Information Command The Request ID Information command may be transmitted as either a DSI long command structure or a DSI short command structure of any length. The data field in the command structure is ignored but is included in the CRC calculation. No action is taken by MMA81XXEG/MMA82XXEG if this command is sent to the DSI Global Device Address. Table 4-8 Request ID Information Command Structure Address A3 A3 A2 A2 A1 A1 A0 A0 C3 0 Command C2 1 C1 0 C0 0 0 to 8 bits CRC Table 4-9 Short Response Structure - Request ID Information Command Response Length Response D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 V2 V1 V0 0 0 1 0 0 Table 4-10 Long Response Structure - Request ID Information Command Data CRC D15 A3 D14 A2 D13 A1 D12 A0 D11 0 D10 0 D9 0 D8 0 D7 V2 D6 V1 D5 V0 D4 0 D3 0 D2 1 D1 0 D0 0 0 to 8 bits 4.6.2 Clear Command The Clear command may be transmitted as either a DSI long command structure or a DSI short command structure of any length. The data field in the command structure is ignored but is included in the CRC calculation. Table 4-11 Clear Command Structure Address A3 A3 A2 A2 A1 A1 A0 A0 C3 0 Command CRC C2 1 C1 1 C0 1 0 to 8 bits When a Clear Command is successfully decoded and the address field matches either the assigned device address or the DSI Global Device Address, the bus switch is opened and the device undergoes a full reset operation. There is no response to the Clear Command. MMA81XXEG Sensors Freescale Semiconductor 23 4.6.3 Read/Write NVM Command The Read/Write NVM command must be transmitted as a DSI long command structure. No action is taken by MMA81XXEG/ MMA82XXEG if this command is sent to the DSI Global Device Address. Table 4-12 Read Write NVM Command Structure Data D7 RA3 D6 RA2 D5 RA1 D4 RA0 D3 RD3 D2 RD2 D1 RD1 D0 RD0 A3 A3 Address A2 A2 A1 A1 A0 A0 C3 1 Command CRC C2 0 C1 0 C0 1 0 to 8 bits Table 4-13 Long Response Structure - Read/Write NVM Command (NV = 1) Data CRC D15 A3 D14 A2 D13 A1 D12 A0 D11 RA3 D10 RA2 D9 RA1 D8 RA0 D7 1 D6 1 D5 B1 D4 B0 D3 RD3 D2 RD2 D1 RD1 D0 RD0 0 to 8 bits Table 4-14 Long Response Structure - Read/Write NVM Command (NV = 0) Data CRC D15 A3 D14 A2 D13 A1 D12 A0 D11 0 D10 0 D9 0 D8 0 D7 1 D6 1 D5 1 D4 1 D3 A3 D2 A2 D1 A1 D0 A0 0 to 8 bits There is no response if the Read/Write NVM Command is received within a DSI short command structure. OTP data are accessed by fields, where a field is a combination of register address (RA3 - RA0) and bank select (B1, B0) bits. Bank select bits are assigned during an Initialization or Reverse Initialization command. Individual bits with predefined functions (the upper four bits of DEVCFG2) each have their own field address. The remaining OTP data are grouped into four-bit fields. Field addresses are shown in Table 4-15. The structure of the OTP array results in data being programmed in 16-bit groups. DEVCFG1 and DEVCFG2 are in the same group. As a result, a non-zero device address assigned during Initialization or Reverse Initialization will be permanently programmed into the OTP array when any field within the two device configuration bytes is programmed. To avoid programming a non-zero device address, ensure that device address 0 is assigned during Initialization or Reverse Initialization before programming any other bit(s) in DEVCFG1 or DEVCFG2. OTP programming operations occur when the Read/Write NVM command is executed after the NV bit has been set during a preceding Initialization or Reverse Initialization command. The minimum DSI Bus idle voltage must exceed 14 V when programming the OTP array. When this command is executed while the NV bit is cleared, the DSI device address will be returned regardless of the state of the register address and bank select bits. The Read Register Data command (described in Section 4.6.5) may be used to access the full range of customer accessible data. MMA81XXEG 24 Sensors Freescale Semiconductor Table 4-15 OTP Field Assignments Register Address RA3 0 RA2 1 RA1 1 RA0 0 Bank Select Register B1 0 1 0 1 1 1 0 0 1 1 1 0 0 0 0 1 1 0 0 1 0 1 1 0 1 0 0 1 1 0 1 1 0 1 1 1 0 0 0 1 1 1 0 1 0 1 1 1 1 0 0 1 1 1 1 1 0 1 1 B0 1 0 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DEVCFG1[3:0] DEVCFG1[7:4] DEVCFG2[7] DEVCFG2[3:0] DEVCFG2[5] DEVCFG2[6] REG8[3:0] REG8[7:4] REG9[3:0] REG9[7:4] REGA[3:0] REGA[7:4] REGB[3:0] REGB[7:4] REGC[3:0] REGC[7:4] REGD[3:0] REGD[7:4] REGE[3:0] REGE[7:4] REGF[3:0] REGF[7:4] DEVCFG[4] DDIS User Defined User Defined User Defined User Defined User Defined User Defined User Defined LOCK2 DSI Bus Device Address GLDE PAR2 User Defined User Defined Definition 4.6.4 Format Control Command The Format Control command must be transmitted as a DSI long command structure. No change to the format registers occurs if the Format Control Command is received within a DSI short command structure. If this command is sent to the DSI Global Device Address, the format registers are updated, however there is no response. The Format Control command conforms to the DSI 2.0 Specification. Table 4-16 Format Control Command Structure Data D7 R/W D6 FA2 D5 FA1 D4 FA0 D3 FD3 D2 FD2 D1 FD1 D0 FD0 A3 A3 Address A2 A2 A1 A1 A0 A0 C3 1 Command CRC C2 0 C1 1 C0 0 0 to 8 bits 4.6.4.1 Format Register Read/Write Control Bit (R/W) 1 - Write Format Control register selected by FA2 - FA0 0 - Read Format Control register unless global command MMA81XXEG Sensors Freescale Semiconductor 25 4.6.4.2 Format Control Register Selection (FA2 - FA0) This three-bit field selects one of eight format control registers. Format control registers are described in Section 4.6.4.3. Table 4-17 Long Response Structure - Format Control Command Data CRC D15 A3 D14 A2 D13 A1 D12 A0 D11 0 D10 1 D9 1 D8 0 D7 R/W D6 FA2 D5 FA1 D4 FA0 D3 FD3 D2 FD2 D1 FD1 D0 FD0 0 to 8 bits There is no response if the Format Control Command is received within a DSI short command structure. 4.6.4.3 Format Control Registers The seven 4-bit format control registers defined in the DSI 2.0 Bus Specification are shown in Table 4-18 below. The default values assigned to each register following reset are indicated. Table 4-18 Format Control Registers Format Control Register Default Value Address Name Decimal CRC Polynomial - Low Nibble CRC Polynomial - High Nibble Seed - Low Nibble Seed - High Nibble CRC Length (0 to 8) Short Word Data Length (8 to 15) Reserved Format Selection 0 1 2 3 4 5 6 7 FA2 0 0 0 0 1 1 1 1 FA1 0 0 1 1 0 0 1 1 FA0 0 1 0 1 0 1 0 1 FD3 0 0 1 0 0 1 0 0 FD2 0 0 0 0 1 0 0 0 FD1 0 0 1 0 0 0 0 0 FD0 1 1 0 0 0 0 0 0 The following restrictions apply to format control register operations, in accordance with the DSI 2.0 Bus Specification: * * * Attempting to write a value greater than eight to the CRC Length Register will cause the write to be ignored. The contents of the register will remain unchanged. Attempting to write a value less than eight to the Short Word Data Length register will cause the write to be ignored. The contents of the register will remain unchanged. The contents of the Format Selection register determine whether standard DSI values or the values contained in the remaining format control registers will be used. The values contained in the remaining format control registers become effective when this register is successfully written to `1111'. If the register is currently cleared, and one of the data bits FD3 - FD0 is not received as a logic `1', the data in the register will remain all zeroes and the device will continue to use standard DSI format settings. If the register bits FD3 - FD0 are all set and one of the bits is received as a logic `0' value, the data in the register will remain `1111' and the values contained in the remaining format control registers will continue to be used. MMA81XXEG 26 Sensors Freescale Semiconductor 4.6.5 Read Register Data Command The Read Register Data command must be transmitted as a DSI long command structure. Table 4-19 Read Register Data Command Structure Data D7 0 D6 0 D5 0 D4 0 D3 RA3 D2 RA2 D1 RA1 D0 RA0 A3 A3 Address A2 A2 A1 A1 A0 A0 C3 1 Command CRC C2 0 C1 1 C0 1 0 to 8 bits Table 4-20 Long Response Structure - Read Register Data Command Data CRC D15 A3 D14 A2 D13 A1 D12 A0 D11 RA3 D10 RA2 D9 RA1 D8 RA0 D7 RD7 D6 RD6 D5 RD5 D4 RD4 D3 RD3 D2 RD2 D1 RD1 D0 RD0 0 to 8 bits There is no response if the Read Register Data Command is received within a DSI short command structure or if this command is sent to the DSI Global Device Address. The sixteen registers shown in Table 3-1 may be accessed using this command. Register address combinations are listed below. Table 4-21 Read Register Data Command Address Assignment RA3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RA2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RA1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RA0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Register SN0 SN1 SN2 SN3 TYPE Reserved DEVCFG1 DEVCFG2 REG-8 REG-9 REG-A REG-B REG-C REG-D REG-E REG-F MMA81XXEG Sensors Freescale Semiconductor 27 4.6.6 Disable Self-Test Stimulus Command The Disable Self-Test Stimulus command may be transmitted as either a DSI long command structure or a DSI short command structure of any length. The data field in the command structure is ignored but is included in the CRC calculation. Table 4-22 Disable Self-Test Stimulus Command Structure Address A3 A3 A2 A2 A1 A1 A0 A0 C3 1 Command CRC C2 1 C1 0 C0 0 0 to 8 bits Table 4-23 Short Response Structure - Disable Self-Test Stimulus Command Response Length Response D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 NV U ST BS AT1 AT0 S GF Table 4-24 Long Response Structure - Disable Self-Test Stimulus Command Data CRC D15 A3 D14 A2 D13 A1 D12 A0 D11 0 D10 0 D9 0 D8 0 D7 NV D6 U D5 ST D4 BS D3 AT1 D2 AT0 D1 S D0 GF 0 to 8 bits This command will execute if either the device specific address or DSI global device address (address $0) is provided. A secondary function, self-test lockout, is activated when two consecutive Disable Self-Test Stimulus commands are received. Following self-test lockout, the internal self-test circuitry is disabled until a Clear command is received or the device undergoes power-on reset. 4.6.7 Enable Self-Test Stimulus Command The Enable Self-Test Stimulus command may be transmitted as either a DSI long command structure or a DSI short command structure of any length. The data field in the command structure is ignored but is included in the CRC calculation. No action is taken by the device if this command is sent to the DSI Global Device Address. Table 4-25 Enable Self-Test Stimulus Command Structure Address A3 A3 A2 A2 A1 A1 A0 A0 C3 1 Command CRC C2 1 C1 0 C0 1 0 to 8 bits MMA81XXEG 28 Sensors Freescale Semiconductor Table 4-26 Short Response Structure - Enable Self-Test Stimulus Command Response Length Response D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 NV U ST BS AT1 AT0 S GF Table 4-27 Long Response Structure - Enable Self-Test Stimulus Command Data CRC D15 A3 D14 A2 D13 A1 D12 A0 D11 0 D10 0 D9 0 D8 0 D7 NV D6 U D5 ST D4 BS D3 AT1 D2 AT0 D1 S D0 GF 0 to 8 bits If self-test locking has been activated, the ST bit will be cleared in the response from the device. Self-Test locking is described in Section 4.6.6. 4.6.8 Reverse Initialization Command The reverse initialization command conforms to the description provided in Section 6.2.1 of the DSI Bus Standard, Version 2.0. At power-up the device is fully compliant with the DSI 1.1 protocol. The initialization command must be transmitted as a DSI 1.1 compliant long command structure. Features of the DSI 2.0 protocol can not be accessed until a valid DSI 1.1 compliant initialization sequence is performed and the enhanced mode format registers are properly configured. Table 4-28 Reverse Initialization Command Structure Data D7 NV D6 BS D5 B1 D4 B0 D3 PA3 D2 PA2 D1 PA1 D0 PA0 A3 A3 Address A2 A2 A1 A1 A0 A0 C3 1 Command CRC C2 1 C1 1 C0 1 4 bits Figure 4-1 illustrates the sequence of operations performed following negation of internal power-on reset (POR) and execution of a DSI Reverse Initialization command. Reverse Initialization commands are recognized only at BUSOUT. The BUSIN node is tested for a bus short to battery high voltage condition, and the bus fault (BF) flag set if an error condition is detected. If no bus fault condition is detected and the BS bit is set in the command structure, the bus switch will be closed. If the device has been pre-programmed, PA3 - PA0 and A3 - A0 must match the pre-programmed address. If no device address has been previously programmed into the OTP array, PA3 - PA0 contain the device address, while A3 - A0 must be zero. If any addressing condition is not met, the device address is not assigned, the bus switch will remain open and the device will not respond to the Reverse Initialization command. If the BS bit is set, the DSI bus voltage level is disregarded for approximately 180 s following reverse initialization to allow hold capacitors on downstream slaves to charge. Table 4-29 Long Response Structure - Reverse Initialization Command Data CRC D15 A3 D14 A2 D13 A1 D12 A0 D11 0 D10 0 D9 0 D8 BF D7 NV D6 BS D5 B1 D4 B0 D3 A3 D2 A2 D1 A1 D0 A0 4 bits In the response, bits D15 - D12 and D3 - D0 will contain the device address. If the device was unprogrammed when the reverse initialization command was issued, the device address is assigned as the command executes. Both fields will contain the value PA3 - PA0 to indicate successful device address assignment. Initialization or reverse initialization commands which attempt to assign device address zero are ignored. MMA81XXEG Sensors Freescale Semiconductor 29 SECTION 5 PERFORMANCE SPECIFICATIONS 5.1 MAXIMUM RATINGS Maximum ratings are the extreme limits to which the device can be exposed without permanently damaging it. The device contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table below. Table 5-1 Ref 1 2 Supply Voltages HCAP BUSIN, BUSOUT Rating Symbol VHCAP VBUS VPP/TEST VIN VGND IIN IIN I gmax gmax gmax gpms gshock hDROP VESD VESD VESD Tstg TJ Value -0.3 to +40 -0.3 to +40 -0.3 to +11 -0.3 to +3.0 -0.3 to +3.0 400 200 10 1400 950 2200 1500 2000 1.2 2000 500 200 -40 to +125 -40 to +150 Unit V V V V V mA mA mA g g g g g m V V V C C (3) (3) (3) (3) (3) (3) (3) (3) (3) (3) (3) (3) (3) (3) (3) (3) (3) (3) (3) 3 Voltage at Programming/Test Mode Entry pin 4 Voltage at CREG, DIN, CLK, CFIL, DOUT 5 Voltage at VGND 6 7 BUSIN, BUSOUT, BUSRTN and HCAP Current Maximum duration 1 s Continuous 8 Current Drain per Pin Excluding VSS, BUSIN, BUSOUT, BUSRTN 9 10 11 Acceleration (without hitting internal g-cell stops) Z-axis g-cell X-axis g-cell (40g, 70g) X-axis g-cell (100g - 250g) 12 Powered Shock (six sides, 0.5 ms duration) 13 Unpowered Shock (six sides, 0.5 ms duration) 14 Drop Shock (to concrete surface) 15 16 17 18 19 1. 2. 3. 4. Electrostatic Discharge Human Body Model (HBM) Charge Device Model (CDM) Machine Model (MM) Temperature Range Storage Junction Parameters tested 100% at final test. Parameters tested 100% at unit probe. Verified by characterization, not tested in production. (*) Indicates a customer critical characteristic or Freescale important characteristic. MMA81XXEG 30 Sensors Freescale Semiconductor 5.2 Ref 20 THERMAL CHARACTERISTICS Characteristic Thermal Resistance Symbol JA JC Min -- -- Typ -- -- Max 85 46 Units C/W C/W (3) (3) 5.3 OPERATING RANGE The operating ratings are the limits normally expected in the application and define the range of operation. Ref 21 22 Characteristic Supply Voltage (Note 9) VHCAP (Note 5) BUSIN, BUSOUT Symbol VHCAP VBUS Min VL 6.3 -0.3 Typ -- -- Max VH 30 30 Units V V (1) (1) VHCAP Undervoltage Detection (see Figure 5-1) Undervoltage Detection Threshold 23 VHCAP Recovery Threshold 24 25 Hysteresis (VLVR - VLVD) CREG Undervoltage Detection (see Figure 5-2) Undervoltage Detection Threshold 26 CREG Recovery Threshold 27 28 Hysteresis (VLVR - VLVD) 29 Test Mode Activation Voltage Programming Voltage 30 via SPI 31 via DSI 32 OTP Programming Current 33 1. 2. 3. 4. 5. 6. Operating Temperature Range Standard Temperature Range VLVD VLVR VLVH VLVD VLVR VLVH VTEST VPP/TEST VBUS IPROG TA -- -- -- -- -- -- 4.5 7.5 14 -- TL -40 -- -- 100 2.25 2.35 100 -- 8.0 -- -- -- 6.2 6.3 -- -- -- -- 10 8.5 30 85 TH +125 V V mV V V mV V V V mA C (1) (1) (3) (3) (3) (3) (3) (3) (3) (3) (6) Parameters tested 100% at final test. Parameters tested 100% at unit probe. Verified by characterization, not tested in production. (*) Indicates a customer critical characteristic or Freescale important characteristic. Minimum operating voltage may be reduced pending characterization. Device fully characterized at +105 C and +125 C. Production units tested +105 C, with operation at +125 C guaranteed through correlation with characterization results. 9. Maximum voltage characterized. Minimum voltage tested 100% at final test. Maximum voltage tested 100% to 24 V at final test. MMA81XXEG Sensors Freescale Semiconductor 31 5.4 ELECTRICAL CHARACTERISTICS The unit digit is defined to be 1 least significant bit (LSB) of the 10-bit digital value, or 1 LSB of the equivalent 8-bit value if explicitly stated. VL (VBUS - VSS) VH, VL (VHCAP - VSS) VH,TL TA TH, unless otherwise specified. . Ref Characteristic Digital Output Sensitivity 20g Range 40g Range 50g Range 100g Range 150g Range 250g Range CFIL Output Sensitivity (TA = 25 C) 20g Range 40g Range 50g Range 100g Range 150g Range 250g Range Sensitivity Error TA = 25 C TL TA TH Offset (measured in 0g orientation) TA = 25 C (8-bit) TL TA TH (8-bit) TA = 25 C (10-bit) TL TA TH (10-bit) Full-Scale Range, including sensitivity and offset errors 20g Range 40g Range 50g Range 100g Range 150g Range 250g Range Range of Output Normal (10-bit) Normal (8-bit) Fault Nonlinearity Measured at CFIL output, TA = 25 C Symbol Min Typ Max Units 34 35 36 37 38 39 40 41 42 43 44 45 46 47 * * * * * * * * * * * * * * SENS SENS SENS SENS SENS SENS SENS SENS SENS SENS SENS SENS SENS SENS OFF8 OFF8 OFF10 OFF10 FSR FSR FSR FSR FSR FSR -- -- -- -- -- -- -- -- -- -- -- -- -5 -7 0.0488 0.0976 0.122 0.244 0.366 0.610 20.1 10.0 8.02 4.01 2.67 1.60 0 0 -- -- -- -- -- -- -- -- -- -- -- -- +5 +7 g/digit g/digit g/digit g/digit g/digit g/digit mV/V/g mV/V/g mV/V/g mV/V/g mV/V/g mV/V/g % % (7) (7) (7) (7) (7) (7) (3) (3) (3) (3) (3) (3) (1) (1) 48 49 50 51 * * 122 116 488 464 128 128 512 512 134 140 536 560 digit digit digit digit (7) (7) (1) (1) 52 53 54 55 56 57 21.0 42.0 52.5 105 158 263 24.9 49.9 62.3 124.7 187 312 26.6 53.4 66.7 133 200 334 g g g g g g (3) (3) (3) (3) (3) (3) 58 59 60 RANGE RANGE FAULT 1 1 -- -- -- 0 1023 255 -- digit digit digit (3) (3) (8) 61 62 63 64 NLOUT VCREG REGLINE REGLOAD RR CREG ESR -1 0 +1 % (3) Internal Voltage Regulator Output Voltage Line regulation Load regulation (IREG < 6 mA) Ripple rejection (DC fRIPPLE 10 kHz, CREG 0.9 F) 65 66 CREG capacitance 67 Effective series resistance, CREG capacitor 1. 2. 3. 4. 7. 8. 2.37 -- 0.45 60 0.9 -- 2.5 -- -- -- -- -- 2.63 6 2 -- -- 700 V mV mV/mA dB F m (1) (3) (3) (3) (3) (3) Parameters tested 100% at final test. Parameters tested 100% at unit probe. Verified by characterization, not tested in production. (*) Indicates a customer critical characteristic or Freescale important characteristic. Tested 100% at 10-bit output. 8-bit value verified via scan. Functionality verified 100% via scan. MMA81XXEG 32 Sensors Freescale Semiconductor 5.5 . Ref ELECTRICAL CHARACTERISTICS (continued) VL (VBUS - VSS) VH, VL (VHCAP - VSS) VH,TL TA TH, unless otherwise specified. Characteristic Input Voltage LOW (CLK,DIN) HIGH (CLK,DIN) Output Voltage (IOUT = 200 A) LOW (DOUT) HIGH (DOUT) Output Loading, CFIL pin (Note 10) Resistance to VCREG, VSS Capacitance to VCREG, VSS Output voltage range * * * Symbol Min Typ Max Units 68 69 VIL VIH VOL VOH RLOAD CLOAD VOUT RSW RFWD IRLKG -- 0.7xVCreg -- VCreg- 0.1 50 -- VSS + 50 mV -- -- -- -- -- 0.3xVCreg -- V V (3) (3) 70 71 -- -- VSS+ 0.1 -- V V (3) (3) 72 73 74 -- -- -- 4.0 -- -- -- 20 VCREG-50mV 8.0 2.5 100 k pF V A (3) (3) (3) (1) (3) (1) 75 Bus Switch Resistance 76 Rectifier Forward Resistance 77 Rectifier Leakage Current BUSIN or BUSOUT to HCAP Rectifier Voltage Drop (VBUS = 26 V) IBUSIN or IBUSOUT = -15 mA IBUSIN or IBUSOUT = -100 mA (VBUS = 7 V) IBUSIN or IBUSOUT = -15 mA IBUSIN or IBUSOUT = -100 mA BUSIN + BUSOUT Bias Current VBUSIN or VBUSOUT = 8.0 V, VHCAP = 9.0 V VBUSIN or VBUSOUT = 0.5 V, VHCAP = 24 V BUSIN and BUSOUT Logic Thresholds Signal Low Signal High BUSIN and BUSOUT Hysteresis Signal Frame BUSIN + BUSOUT Response Current VBUSIN and/or VBUSOUT = 4.0 V 78 79 80 81 * * VRECT VRECT VRECT VRECT -- -- -- -- -- -- -- -- 1.0 1.2 1.0 1.2 V V V V (3) (3) (1) (1) * IBIAS IBIAS * * VTHL VTHH VHYSS VHYSF IRESP * IQ RPD RPD IGNDETC RGNDDETC 309 1 -- -- -- -- 100 20 mA A V V (1) (1) 82 83 84 85 2.7 5.4 3.0 6.0 3.3 6.6 (1) (1) 86 87 * * * 30 100 -- -- 90 300 mV mV (3) (3) 88 9.9 -- 20 11 -- 60 437 12.1 7.5 100 mA mA k k A k (1) (1) (2) (2) 89 Quiescent Current 90 Internal pull-down resistance CLK 91 Internal pull-down resistance VPP/TEST 92 93 1. 2. 3. 4. 10. GND Loss Detect (with external 3 k resistor) Measurement Current Detection Resistance 340 -- 371 10 (1) (1) Parameters tested 100% at final test. Parameters tested 100% at unit probe. Verified by characterization, not tested in production. (*) Indicates a customer critical characteristic or Freescale important characteristic. The external circuit configuration shown in Section 1.3.6 is recommended. MMA81XXEG Sensors Freescale Semiconductor 33 5.6 . Ref ELECTRICAL CHARACTERISTICS (continued) VL (VBUS - VSS) VH, VL (VHCAP - VSS) VH,TL TA TH, unless otherwise specified. Characteristic Total Noise (see Figure 5-3) 400 Hz, 4-pole filter, 20g range RMS, 100 samples P-P, 100 samples 180 Hz, 2-pole filter, 20g range RMS, 100 samples P-P, 100 samples Cross-Axis Sensitivity X-axis, X-axis to Y-axis X-axis, X-axis to Z-axis Y-axis, Y-axis to X-axis Y-axis, Y-axis to Z-axis Analog to digital converter Relative accuracy Differential nonlinearity Gain error Offset error (VIN = VCREG/2) Noise (RMS, 100 samples) Noise (peak) Deflection (Self-Test Output - Offset, average of 30 samples, measured in 0g orientation, TA = 25 C) X-axis, 20g Range X-axis, 40g Range X-axis, 50g Range X-axis, 100g Range X-axis, 150g Range X-axis, 250g Range Z-axis, 40g Range Z-axis, 100g Range Z-axis, 150g Range Z-axis, 250g Range Self-Test deflection range, TA = 25 C, measured in 0g orientation Self-Test deflection range, TL TA TH, measured in 0g orientation Symbol Min Typ Max Units 94 95 96 97 nRMS nP-P nRMS nP-P -- -- -- -- -- -- -- -- 2 8 2 7 digit digit digit digit (3) (3) (3) (3) 98 99 100 101 VXY VXZ VYX VYZ INL DNL GAINERR OFST nRMS nP-P -5 -5 -5 -5 -- -- -- -- +5 +5 +5 +5 % % % % (3) (3) (3) (3) 102 103 104 105 106 107 -2 -1 -1 -3 -1 -3 -- -- -- -- -- -- +2 +1 +1 +3 +1 +3 digit digit %FSR digit digit digit (3) (3) (2) (3) (3) (3) 108 109 110 111 112 113 114 115 116 117 118 * * * * * * * * * * DFLCT DFLCT DFLCT DFLCT DDFLCT DDFLCT DFLCT DFLCT DFLCT DFLCT DFLCT DFLCT -- -- -- -- -- -- -- -- -- -- -10 246 123 98 49 82 49 307 299 205 123 -- -- -- -- -- -- -- -- -- -- -- +10 digit digit digit digit digit digit digit digit digit digit % (7) (7) (7) (7) (7) (7) (7) (7) (7) (7) (1) 119 1. 2. 3. 4. 7. -20 -- +20 % (1) Parameters tested 100% at final test. Parameters tested 100% at unit probe. Verified by characterization, not tested in production. (*) Indicates a customer critical characteristic or Freescale important characteristic. Tested 100% at 10-bit output. 8-bit value verified via scan. MMA81XXEG 34 Sensors Freescale Semiconductor POR NEGATED POR ASSERTED VLVR VLVD VHCAP UNDERVOLTAGE NORMAL OPERATION RESUMES GND UV: UNDERVOLTAGE CONDITION EXISTS VLVH UV UV tUVR Figure 5-1. VHCAP Undervoltage Detection VCREG VLVR VLVD VLVH LOW-VOLTAGE CONDITION DETECTED POR ASSERTED GND Figure 5-2. VCREG Undervoltage Detection POR NEGATED NORMAL OPERATION RESUMES INTERNAL RESET IS INITIALLY ASSERTED UNTIL VCREG VLVR, AND THEREAFTER WHEN VCREG VLVD. MMA81XXEG Sensors Freescale Semiconductor 35 MASTER DOH DOL UUT BUSIN BUSOUT BUSRTN N/C DSI BUS CONFIGURATION D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A3 A2 A1 A0 C3 C2 C1 C0 0 0 0 0 0 0 0 0 0 0 A3 A2 A1 A0 0 0 1 0 COMMAND FORMAT 90 s CMD 1 XXX CMD 2 RESP 1 20 s CMD 3 RESP 2 CMD 99 RESP 98 CMD 100 RESP 99 XXX RESP 100 MEASUREMENT WINDOW (10910 s) MEASUREMENT TIMING Figure 5-3. Total Noise Measurement Conditions MMA81XXEG 36 Sensors Freescale Semiconductor 5.7 CONTROL TIMING VL (VBUS - VSS) VH, VL (VHCAP - VSS) VH,TL TA TH, unless otherwise specified. Ref Characteristic VHCAP Undervoltage Reset Period (see Figure 5-1) VHCAP < VRA to POR assertion Analog to digital converter (see Figure 5-4) Sample time Conversion time Delay following bus idle BUSIN and BUSOUT response current transition 1.0 mA to 9.0 mA, 9.0 to 1.0 mA Initialization to Bus Switch Closing Signal Bit Transition Time Loss of Signal Reset Time Maximum time below frame threshold BUSIN or BUSOUT Timing to Response Current BUSIN or BUSOUT VTHL to IBUS 7 mA BUSIN or BUSOUT VTHH to IBUS 5 mA Interframe Separation Time (see Figure 5-5) Following Read Write NVM Command Following Initialization or Reverse Initialization BS = 1 BS = 0 Following other DSI bus commands Low Pass Filter (4-pole, -3 db Rolloff Frequency) (2-pole, -3 db Rolloff Frequency) Ground Loss Detection Filter Time Cycles of fOSC Time Reset Recovery Time POR negated to Initialization Command POR negated to 180 Hz Data Valid POR negated to 400 Hz Data Valid Internal Oscillator Frequency Logic Duty Cycle Logic `0' Logic `1' OTP Programming, SPI program control Symbol Min Typ Max Units 120 tUVR tSAMPLE tCONVERT tDELAY tITR tBS tBIT tTO tRSPH tRSPL tIFS tIFS tIFS tIFS BWOUT BWOUT tGNDETC tGNDETC tRESET tRESET tRESET fOSC 0.95 1.0 1.05 ms s s s mA/s s s ms s s ms s s s Hz Hz (8) 121 122 123 4.28 7.13 2.85 4.5 7.5 3.0 4.73 7.88 3.15 (8) (8) (8) 124 125 126 4.5 89 5 -- -- -- 7.5 138 200 (3) (3) (3) 127 -- -- 10 (8) 128 129 -- -- -- -- 3.0 3.0 (3) (3) 130 131 132 133 2 200 20 20 -- -- -- -- -- -- -- -- (3) (3) (3) (3) 134 135 360 162 -- 400 180 440 198 -- (1) (1) 136 137 16384 4.096 cycles ms s ms ms MHz (8) (8) 138 139 140 141 -- -- -- 3.80 -- 5.3 2.4 4.0 100 -- -- 4.20 (8) (3) (3) (1) 142 143 144 1. 2. 3. 4. 8. * * DCL DCH tPROG 10 60 -- 33 67 -- 40 90 2 % % ms (8) (8) (8) Parameters tested 100% at final test. Parameters tested 100% at unit probe. Verified by characterization, not tested in production. (*) Indicates a customer critical characteristic or Freescale important characteristics. Functionality verified 100% via scan. Timing is directly determined by internal oscillator frequency. MMA81XXEG Sensors Freescale Semiconductor 37 5.8 CONTROL TIMING (continued) VL (VBUS - VSS) VH, VL (VHCAP - VSS) VH,TL TA TH, unless otherwise specified. Ref Characteristic SPI Timing (see Figure 5-6) CLK period DIN to CLK setup CLK to DIN hold CLK to DOUT Sensing Element Resonant Frequency Z-axis g-cell X-axis medium-g g-cell (20-50g) X-axis high-g g-cell (100-250g) Sensing Element Rolloff Frequency (-3 db) Z-axis g-cell X-axis medium-g g-cell (20-50g) X-axis high-g g-cell (100-250g) Gain at Package Resonance Z-axis X-axis Package Resonance Z-axis X-axis Symbol Min Typ Max Units 145 146 147 148 tCLK tDC tCDIN tCDOUT fGCELL fGCELL fGCELL BWGCELL BWGCELL BWGCELL Q Q 500 50 50 -- -- -- -- -- -- -- -- 20 ns ns ns ns (3) (3) (3) (3) 149 150 151 -- 11.2 18.0 22.0 12.8 20.6 -- 15.3 24.2 kHz kHz kHz (3) (3) (3) 152 153 154 -- -- -- 1.58 19 32 -- -- -- kHz kHz kHz (3) (3) (3) 155 156 -- -- 10 12 -- -- kHz kHz (3) (3) 157 158 1. 2. 3. 4. 8. f f -- -- 45 9.5 -- -- kHz kHz (3) (3) Parameters tested 100% at final test. Parameters tested 100% at unit probe. Verified by characterization, not tested in production. (*) Indicates a customer critical characteristic or Freescale important characteristics. Functionality verified 100% via scan. Timing is directly determined by internal oscillator frequency. MMA81XXEG 38 Sensors Freescale Semiconductor BUSIN tSAMPLE tDELAY STABILIZATION S/H tCONVERT CONVERSION Figure 5-4. A-to-D Conversion Timing DSI BUS COMMAND BUSIN tIFS Figure 5-5. DSI Bus Interframe Timing tCLK CLK tDC DIN/VGND tCDOUT DOUT DATA VALID tCDIN Figure 5-6. Serial Interface Timing MMA81XXEG Sensors Freescale Semiconductor 39 APPENDIX A TEST MODE OPERATION Test mode is entered when certain conditions are satisfied after power is applied to the device. Communication with the device is conducted using the SPI when in test mode. Two test mode operations are of interest to the customer. These operations are described below. Test mode communication is conducted using the serial peripheral interface (SPI). A.1 SPI DATA TRANSFER A 16-bit SPI is available for data transfer when the voltage at VPP/TEST is raised above VTEST. Test mode is entered when the sequence of data values shown above are transferred following reset. See Figure A-4 for details of 16-bit SPI packet. The state of DIN is latched on the rising edge of CLK. DOUT changes on the falling edge of CLK. The interface conforms to CPHA = 0, CPOL = 0 operation for conventional SPI devices. A.2 ADC TEST MODE A special device configuration useful for evaluating the performance of the analog-to-digital convertor block is available. When selected, internal buffers which drive the CFIL pin and ADC input are disabled, and the input of the ADC is connected to the CFIL pin, as illustrated in Figure A-1. The following sequence of operations must be performed to enter ADC Test Mode. Refer to Appendix A.4 for details regarding register read and write operations. 1. 2. 3. 4. 5. Apply VHCAP to the HCAP pin. This may be accomplished through BUSIN if desired. Apply VTEST to the VPP/TEST pin. Transfer the data value $AA to device register address $30 via the SPI. Transfer the data value $55 to device register address $30 via the SPI. Transfer the data value $1D to device register address $30 via the SPI. Remove power or lower the voltage at VPP/TEST to exit ADC Test Mode. MMA81XXEG 40 Sensors Freescale Semiconductor REGULATOR TRIM 11 VOLTAGE REGULATOR INTERNAL SUPPLY VOLTAGE 9 HCAP CREG 3 12 CREG BUSOUT BUSIN 13 N/C N/C 1 2 VSS VSS VSS BUSRTN BANDGAP REFERENCE 16 15 10 14 GROUND LOSS DETECTOR 7 VGND/DIN OSCILLATOR SELFTEST TRIM OSC TRIM SELFTEST VOLTAGE LOGIC COMMAND DECODE STATE MACHINE RESPONSE GENERATION 4 OTP PROGRAMMING INTERFACE 6 8 VPP/TEST DOUT CLK SELF-TEST ENABLE A-TO-D CONVERTER g-CELL C-TO-V CONVERTER LOW-PASS FILTER 5 CFIL GAIN TRIM OFFSET TRIM TCS TRIM Figure A-1. ADC Test Mode Configuration MMA81XXEG Sensors Freescale Semiconductor 41 A.3 OTP PROGRAMMING OPERATIONS The ten customer-programmed OTP locations (DEVCFG0, DEVCFG1 and REG-8 through REG-F) may be programmed when the device is in test mode if the following sequence of operations is performed. Register access operations required for OTP programming are described in Appendix A.4. 1. 2. 3. 4. 5. 6. 7. 8. 9. Apply VHCAP to the HCAP pin. This may be accomplished through BUSIN if desired. Apply VTEST to the VPP/TEST pin. Write the desired data values to the two registers via the SPI. Transfer the data value $AA to device register address $30 via the SPI. Transfer the data value $55 to device register address $30 via the SPI. Transfer the data value $C6 to device register address $30 via the SPI. Write the data value $00 to address $20 via the SPI. This will enable write access to the fuse mirror registers. Write register data to be programmed into fuse array. Write the data value $05 to address $20 via the SPI. The automatic programming sequence is initiated by this write operation. 10. Delay a minimum of 32 s to allow the programming sequence to begin. 11. Read data value from address $29 until bit 5 is set. 12. If bit 4 of value read from address $29 is set, the programming operation did not complete successfully. Bits which are unprogrammed may be programmed to a logic `1' state. The device may be incrementally programmed if desired, however once a bit is programmed to a logic `1' state, it may not be reset to logic `0' in the OTP array. Once the LOCK2 bit has been set, no further changes to the OTP array are possible. Setting LOCK2 also enables parity detection when the device operates in normal mode. A.4 * * * INTERNAL REGISTER ACCESS Program the OTP memory Read the OTP memory Access various internal signals of the MMA81XXEG/MMA82XXEG in Test mode CLK DOUT DIN/VGND SERIAL PERIPHERAL INTERFACE REGISTER ARRAY TO DIGITAL INTERFACE Using the DIN /VGND, CLK, and DOUT pins, each address location of MMA81XXEG/MMA82XXEG can be read and written from an external SPI interface shown in Figure A-2. The corresponding registers may be used to: OTP ARRAY Figure A-2. OTP Interface Overview MMA81XXEG 42 Sensors Freescale Semiconductor A.4.1 Interface Data Bit Stream The 16-bit SPI serial data consists of 6 bits for a data address, 1 bit for a data direction, and 8 bits for the data to be transferred as shown below. BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FUNCTION A[5] A[4] A[3] A[2] A[1] A[0] RW D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Figure A-3. Serial Data Stream A[5:0] Register array location to be read or written. D[7:0] Register array data. This is the data to be transferred to the register array during write operations, or the data contained in the array at the associated address during read operations. RW Control of data direction during the clocking of D[7:0] data bits as follows: RW = 1 Register array write. D[7:0] are transferred into the register array during subsequent transitions of the CLK input. RW = 0 Register array read. Data are transferred from the register array during subsequent transitions of the CLK input. A.4.2 Register Array Read Operation Read operations are completed through16-bit transfers using the SPI as shown below. Data contained in the array at the associated address are presented at the DOUT pin during the 8th through 15th falling edges at the CLK input. 1 CLK DIN/VP2 DOUT A[5] A[4] A[3] A[2] A[1] A[0] RW D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Figure A-4. Serial Data Timing, Register Array Read Operation Should the data transfer be corrupted by e.g., noise on the clock line, a device reset is required to restore the state of internal logic. MMA81XXEG Sensors Freescale Semiconductor 43 A.4.3 Register Array Write Operation A write operation is completed through the transfer of a 16-bit value using the SPI as shown in the diagram below. Data present at the DIN pin are transferred to the register at the associated address during the 9th through 16th rising edges at the CLK input. Contents of the register at the time the write operation is initiated are presented at the DOUT pin during the 8th through 15th falling edges of the CLK input. 1 CLK DIN/VP2 DOUT A[5] A[4] A[3] A[2] A[1] A[0] RW D[7] D[7] D[6 D[5] D[4] D[3] D[2] D[1] D[0] D[6] D[5] D[4] D[3] D[2] D[1] D[0] 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Figure A-5. Serial Data Timing, Register Array Write Operation A.4.4 Internal Address Map Overview OTP data is transferred to internal registers during the first sixteen clock cycles following oscillator startup and negation of internal reset. When the device operates in test mode, OTP data in the mirror registers may be overwritten. Mirror register writes must be enabled by setting the SPI_WRITE_ENABLE bit (address $29[5]). This bit may be set by writing the value $0 to address $20. Internal register read and write operations are described in Section 3. MMA81XXEG 44 Sensors Freescale Semiconductor PACKAGE DIMENSIONS MMA81XXEG Sensors Freescale Semiconductor 45 PACKAGE DIMENSIONS MMA81XXEG 46 Sensors Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. 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Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc., 2009. All rights reserved. RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http:/www.freescale.com or contact your Freescale sales representative. For information on Freescale's Environmental Products program, go to http://www.freescale.com/epp. MMA81XXEG Rev.4 9/2009 |
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